esd5341n will semiconductor ltd. 1 revision 1 .4 , 201 7/ 0 5 / 13 esd 534 1n 1 - line , un i - d irectional, l ow capacitance trans ient voltage suppressor descriptions the esd53 4 1n is a low capacitance tvs (tran sient voltage suppressor) designed to protect high speed data interfaces. it has been specifically designed to protect sensitive electronic components which are connected to data and transmission lines from over - stress caused by esd (e lectro s tatic d ischarge ) . the esd53 4 1n incorporates one pair of low capacitance steering diodes plus a tvs diode. the esd53 4 1n may be used to provide esd protection up to 2 0 k v (contact discharge ) according to iec61000 - 4 - 2 , and withstand peak pulse current up to 4 a ( 8/20 s ) according to iec61000 - 4 - 5. the esd53 4 1n is available in dfn1006 - 2l package. standard products are pb - free and halogen - fr ee. features ? stand - off voltage: 5 v m ax . ? transient protection for each line according to iec61000 - 4 - 2 (esd) : 2 0 k v ( contact discharge ) iec61000 - 4 - 4 (eft): 40a (5/50ns ) iec61000 - 4 - 5 (surge): 4 a (8/20 s) ? l ow capacitance: c j = 1.0 pf typ. ? ultra - low leakage cu rrent: i r <1 na typ. ? l ow clamping voltage : v cl = 1 8 v t yp. @ i pp = 16a (tlp) ? solid - state silico n technology applications ? usb interface ? hdmi interface ? dvi ? portable electronics ? notebooks h ttp // : www. sh - willsemi.com dfn1006 - 2 l (bottom v iew) circuit diagram 7 = device code * = month code ( a~z) marking (top view) order i nformation device package shipping esd53 4 1n - 2/tr dfn1006 - 2l 10 000/tape&reel p i n 1 p i n 2 7 * . p i n 1 p i n 2
esd5341n will semiconductor ltd. 2 revision 1 .4 , 201 7/ 0 5 / 13 absolute m aximum r ating s electrical characteristics (t a = 25 o c, unless otherwise noted) notes: 1) tlp parameter: z 0 = 50 , t p = 100ns, t r = 2n s, averaging window from 60ns to 80ns. r dyn is calculated fr om 4a to 16a. 2) non - repetitive current pulse, according to iec61000 - 4 - 5. parameter symbol rating unit peak pulse powe r ( t p = 8/20 s) p pk 60 w peak pulse current (t p = 8/20 s) i pp 4 a esd according to iec61000 - 4 - 2 air discharge v esd 2 0 k v esd according to iec61000 - 4 - 2 contact discharge 2 0 j unction t emperature t j 1 25 o c operating temperature t op - 40 ~ 85 o c lead te mperature t l 260 o c storage temperature t stg - 55~150 o c parameter symbol condition min. typ. max. unit rever se maximum working voltage v rwm 5.0 v rever se leakage current i r v rwm = 5 v <1 1 00 n a rever se breakdown voltage v br i t = 1ma 7.0 8. 0 9.0 v forward voltage v f i t = 1 0ma 0.6 0. 9 1.2 v clamping voltage 1) v cl i pp = 16a, t p = 100ns 1 8 .0 v dynamic resistance 1) r dyn 0. 6 clamping voltage 2 ) v cl i pp = 1a, t p = 8/20s 11 v i pp = 4 a, t p = 8/20s 1 5 v junction capacitance c j v r = 0v, f = 1mhz 1.0 1.4 pf
esd5341n will semiconductor ltd. 3 revision 1 .4 , 201 7/ 0 5 / 13 typical characteristics ( t a = 25 o c, unless otherwise noted ) 8/20 s w aveform per iec61000 - 4 - 5 clamping voltage vs. peak pulse c urrent non - repetitive peak pulse p ower vs. pulse time contact discharge current waveform per iec61000 - 4 - 2 capacitance vs. rever se voltage power derating vs. ambient t emperature 0 1 2 3 4 5 0.8 0.9 1.0 1.1 1.2 f = 1mhz v ac = 50mv c j - junction capacitance (uniformization) v r - reverse voltage (v) 1 10 100 1000 1 10 100 1000 peak pulse power (w) pulse time ( ? s) 0 25 50 75 100 125 150 0 20 40 60 80 100 % of rated power t a - ambient temperature ( o c) 0 1 2 3 4 5 8 10 12 14 pulse waveform: t p = 8/20 ? s v c - clamping voltage (v) i pp - peak pulse current (a) t 60ns 30ns t r = 0.7~1ns 10 90 100 current (%) time (ns) 0 0 100 20 90 50 10 t 2 t 1 front time: t 1 = 1.25 ? ? t = 8 ? s time to half-value: t 2 = 20 ? s peak pulse current (%) time ( ? s) t
esd5341n will semiconductor ltd. 4 revision 1 .4 , 201 7/ 0 5 / 13 typical c haracteristics ( t a = 25 o c, unless otherwise noted ) esd clamping ( +8kv contact discharge per iec61000 - 4 - 2) tlp measurement esd clamping ( - 8kv contact discharge per iec61000 - 4 - 2 ) 0 2 4 6 8 10 12 14 16 18 20 22 -2 0 2 4 6 8 10 12 14 16 18 20 z 0 = 50 ? t r = 2ns t p = 100ns tlp current (a) tlp voltage (v)
esd5341n will semiconductor ltd. 5 revision 1.4, 2017/05/13 package outline dimensions dfn1006-2l top view bottom view side view recommended pcb layout (unit: mm) symbol dimensions in millimeters min. typ. max. a 0.340 0.450 0.530 a1 0.000 0.020 0.050 a3 0.125 ref. d 0.950 1.000 1.075 e 0.550 0.600 0.675 b 0.200 0.250 0.300 l 0.450 0.500 0.550 e 0.650 bsc cathode marking d e a3 a1 a () () () () () e b l notes: this recommended land pattern is for reference purposes only. please consult your manufacturing group to ensure your pcb design guidelines are met. 0.55 0.60 0.85 1.40 0.30
esd5341n will semiconductor ltd. 6 revision 1.4, 2017/05/13 tape and reel information reel dimensions tape dimensions w p1 quadrant assignments for pin1 orientation in tape q1 q2 q4 q3 q1 q2 q4 q3 rd reel dimension ? 7inch ? 13inch w overall width of the carrier tape ? 8mm ? 12mm p pitch between successive cavity centers ? 2mm ? 4mm ? 8mm pin1 pin1 quadrant ? q1 ? q2 ? q3 ? q4 user direction of feed rd
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